CS-704 Important Questions

Question 1: 

In the following code (15)
For (i=2 ; i < 100 ; i = i+1)
{
a[i] = b[i] + a[i] /*s1*/
c[i-1] = a[i] + d[i] /*s2*/
a[i-1] = 2 * b[i] /*s3*/
b[i+1] = 2 * b[i] /*s4*/
}
I. List all dependences (output, anti and true)
II. Indicate whether the true dependences are loop carried or not? III. Why the loop is not parallel?

Question 5:

How many total bits are required for a direct mapped cache with 16 KB of data and 4-word block size, assuming 32-bit address
a) Implementation of directory protocol where the whole directory is centralized in one location have problems scaling to more than a couple hundred processors. what is the bottleneck directory protocol and why does it occur ?How might this bottleneck be removed?
b) How redundancy achieved in RAID system?

Question 3: (Imp )

Determine the path from source address 110 to the destination address 010 for a 3-stage omega topology network ?

Question 4: 

As cache increased in size blocks often increase in size as well ,
a)if a large instruction cache has larger data blocks is there a need for perfetching? Explain the interaction between perfechting and increase block size instruction cache?
b)is there a need for data prefetch instruction when data blocks gets larger ?

Question 4: (Imp + imp +Imp )

The running program pattern
is 0x0 0x8 0x10 0x18 0x20 0x28
a) If you directed mapped cache size 1KB and block size of 8 bytes (2 words)how many set:
b) With the same cache and block size what is miss rate of the directed mapped.
c) On which would decrease miss rate the most
i. Increasing the degree of associative by 2.
ii. Increasing the block size to 16 bytes.

CS704 Paper: 21-8-16

Q: 1 define multiprocessor cache coherence and explain considering three processes which see old values in their caches.
Q: 2 what is cluster SAN? explain performance confronts.
Q: 3
Q:4 or Q: 5

CS704 Time 08:00 Date 25-08-16

Q1: 2D Mesh and 2D Torus
Q2:
Q3: (imp + ) (a) Why the hardware speculation techniques differ from the instruction set extension approach to make the branches predictable at the compile time?
(b) Discuss poison-bit approach used to preserve hardware speculation.

Another Paper

Q1- How speculative instructions handle exception behavior
b- difference between DRAm cell and SRAM cell and Explain Enhanced DRAMs
Q2- Full associative and 2 way associative- it is in solved questions
Q3 was network model
Q4- Koi code tha and had to write branch and conditional code...mujay koi idea nahe ya kahans ay hay
Q5-

Paper copy

Q1 - How construction of fast page mode DRAM differ from normal DRAM ? Explain its working
Q2- How the cache performance can be enhanced by reducing hit time ?
   a) Describe use of pipeline cache access
   b) And trace caches techniques to reduce the hit time.
Q3 -
Q4 -

CS 704 paper 21-08-16 4:30

Shared by Some other CS704 23.08.2016

(b) For an associative cache, a main memory address is viewed as consistency of two fields. List and define the two fields.
(c) Consider the following code sequence:
SW R3, 512 (R0), M[512] - R3
LW R1, 1024(R0); R1 - M[1024]
LW R2, 512(R0),; R2 - M[512]
Assume a direct mapped, write through cache that maps 512 and 1024 to the same block, and a four word write buffer that is not checked on a real miss, Will the value in R2 always be equal to the value in R3?